The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having an improved ESD robustness and a fabrication process thereof.
A semiconductor integrated circuit device generally includes a protection circuit for protecting minute semiconductor elements formed therein from a voltage surge such as the one caused by external electric discharge (ESD).
Because it is preferable to form such a protection circuit with a process similar to the one used for fabricating the semiconductor elements inside the semiconductor integrated circuit device, the protection circuit generally has a construction similar to that of the semiconductor element formed inside the semiconductor integrated circuit device. Further, it is preferable that such a semiconductor element constituting the protection circuit can be used also for an input/output circuit of the semiconductor integrated circuit at the same time.
While there are various ESD protection circuits of different constructions such as the one using a diode or the one using a transistor, FIG. 1 shows an example of a conventional ESD protection circuit 10 that uses a MOS transistor, which constitutes also an input/output circuit. Further, FIG. 2 shows an equivalent circuit diagram of the protection circuit 10 of FIG. 1.
Referring to FIG. 1, the ESD protection circuit 10 includes an n-channel MOS transistor 10A formed on a Si substrate 11 of p−-type, wherein the MOS transistor 10A includes a gate electrode 13 provided on the Si substrate 11 in the state that a gate insulation film 12 is provided between the gate electrode 13 and the Si substrate 11, wherein the Si substrate 11 is further formed with LDD regions 11A and 11B of n−-type at both lateral sides of the gate electrode 13. Further, the Si substrate 11 is formed with diffusion regions 11C and 11D of n+-type formed respectively at further outer sides of the foregoing LDD regions 11A and 11B. Further, sidewall insulation films 13A and 13B are formed at respective lateral sidewall surfaces of the gate electrode 13, and silicide regions 14A and 14B are formed on the surface of the diffusion regions 11C and 11D at respective outer sides of the sidewall insulation films 13A and 13B.
Referring to FIG. 2, the n-channel MOS transistor constitutes a CMOS circuit provided between a power supply line Vdd and a power supply line Vss together with another p-channel MOS transistor having a similar construction, wherein it can be seen that the silicide region 14B of the transistor 10A is connected to an input/output pad 10P.
In the ESD protection circuit 10 of such a construction, the transistors 10A and 10B form an ordinary input/output circuit. Thus, when there comes in a voltage surge to the input/output pad 10P by an ESD or the like in the state the voltage level of the source diffusion region 11C and the voltage level of the gate electrode 13 are set to zero volt, there is caused an increase of voltage level in the diffusion region 11D, and there are formed electron-hole pairs as a result of large potential gradient formed between the n+-type drain region 11D and the substrate 11 of p−-type. Thereby, the holes thus formed are caused to flow to the Si substrate 11 in the form of a hole current Ibh1.
Because of the fact that the Si substrate 11 has a finite resistance, such a discharge current Ibh1 induces an increase of voltage level in the interior of the substrate 11, and as a result, there is caused conduction in a parasitic lateral bipolar transistor, which is formed in the Si substrate 11 by the p-type region 11, n+-type diffusion region 11C and the n+-type diffusion region 11D. Thereby, a large current is caused to flow in the substrate 11 between the diffusion region 11C and the diffusion region 11D as represented in FIG. 1 by an arrow, and the voltage surge is successfully relieved.
FIG. 3 shows the construction of an ESD-protection input/output circuit designed based on the circuitry of FIGS. 1 and 2 for use in an actual semiconductor integrated circuit, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 3, the polysilicon gate electrode 13 has a number of fingers 131-135 extending on the surface of the Si substrate 11, wherein it should be noted that the electrode fingers 131-135 extend over an active region 11Ac, defined on the Si substrate 11 by the device isolation film 11S, in a mutually parallel relationship. Thereby, the n-channel MOS transistor 10 of FIG. 1 is formed in each of the fingers 131-135.
In the construction of FIG. 3, it should further be noted that the drain diffusion region 11D of each MOS transistor 10 is connected to the pad electrode 10P via an interconnection pattern 15. Further, the source diffusion region 11C is connected to the power supply line Vss via the interconnection pattern 16.
By constructing the gate electrode in the form having a large number of branches or fingers, a large number of transistors are connected parallel as represented in FIG. 4, and the ESD protection circuit can handle a large discharge current.
Referring to FIG. 4, it can be seen that, in each of the fingers, the MOS transistor 10A forming the ESD-protection circuit of FIG. 1 is connected to any of the resistors R1-R3 in series connection. According to such a construction, the common node A does not undergo a significant voltage drop even when there has been caused a conduction in any one of the fingers, and thus, the problem of concentration of the discharge current to a particular finger that has caused the conduction first is successfully avoided.
Thus, in the construction having such a ballast resistors, it becomes possible to cause the turning-on of the transistor 10A in all of the fingers in the event of electric surge, and effective protection operation via efficient electric discharge is guaranteed.
Meanwhile, modern, highly miniaturized semiconductor devices achieve improvement of operational speed by forming very thin silicide layers such as the one represented by layers 14A and 14B on the surface of the diffusion regions 11C and 11D as represented in FIG. 1 for reducing the resistance. Thus, in such a structure that uses silicide layers, it is possible to form the ballast resistors R1-R4 of FIG. 4 by merely restricting the area of silicide formation in the vicinity of the channel region, in other words, by forming a silicide block region in which there occurs no silicide formation.
FIG. 5 shows an example of realizing the ballast resistors R1-R5 of FIG. 4 by way of such a silicide block region SBL. In FIG. 5, it should be noted that those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 5, it can be seen that the silicide block region SBL is formed in correspondence to each of the gate electrode fingers 131-135, wherein the silicide block region SBL suppresses the formation of the silicide layers 14A and 14B as explained before.
In the ESD protection device of such a construction, it should be noted that the silicide block region SBL functions as a resistance against the silicide regions 14A and 14B, and it becomes possible to realize the ballast resistors R1-R3 shown in FIG. 4 by way of the silicide block region SBL. Thus, in the ESD protection device of FIG. 5, all the MOS transistors of the fingers 131-135 conduct simultaneously upon incoming of the electric surge, and the problem of concentration of discharge current to a particular transistor is successfully avoided.
Meanwhile, with advancement in the art of device miniaturization, the supply voltage used in recent highly miniaturized semiconductor devices has been lowered from the conventional voltage of 5V to 3.3V. On the other hand, there are still many semiconductor devices that use the supply voltage of 5V, and thus, there is a need for a semiconductor integrated circuit, primarily designed for the supply voltage of 3.3V, that the semiconductor integrated circuit can handle also the input/output signals of 5V.
In order to meet for such a demand, there has been proposed an ESD-protection input/output device as represented in FIG. 6 in which the MOS transistor 10A operable at the supply voltage of 3.3V is cascaded with another MOS transistor 10A′ of the same construction.
FIG. 7 shows the cross-sectional structure of the ESD-protection input/output device of FIG. 6, wherein it should be noted that those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 7, the device of FIG. 6 has a cascaded construction such that the active region 11Ac defined by the device isolation structure 11S includes therein a MOS transistor 10A′ having a gate electrode 13′ in addition to the MOS transistor 10A in cascade connection, such that the MOS transistor 10A′ shares the diffusion region 11D commonly. Further, the MOS transistor 10A′ has an n-type diffusion region 11G at a side opposite to the side of the diffusion region 11D. Further, it is noted that LDD regions 11E and 11F of n−-type are formed at respective inner side regions of the diffusion regions 11D and 11G.
In the ESD-protection input/output device of FIG. 7, it should be noted that there is formed a lateral npn transistor such that the lateral bipolar transistor includes the p-type substrate 11 as a base, the n-type diffusion region 11C as an emitter, and the n-type diffusion region 11G as a collector, wherein the lateral npn transistor causes conduction when a surge voltage comes in to the diffusion region 11G connected to the pad electrode 10P. When conduction occurs, the excessive electric charges are neutralized and the desired ESD protection operation is achieved.
In recent semiconductor integrated circuits having ultrafine semiconductor elements therein, on the other hand, it is becoming difficult to secure sufficient area on the substrate for such ESD-protection devices due to the increase of integration density and associated increase of number of the electrode pads provided on the substrate.
Thus, in such a case of semiconductor integrated circuit devices including ultrafine semiconductor elements, the transistors constituting the ESD-protection input/output device tend to experience severe local heating even if the ESD-protection input/output device has the structure that uses the ballast resistors such as the one shown in FIG. 4 by using the silicide block structure of FIG. 5. When a transistor is destroyed in any of the fingers, the overall current drive capability is reduced for the ESD-protection input/output circuit, and the ESD-protection input/output device can no longer provide sufficient protection against ESD.
Further, in the case of the cascaded circuit such as the one shown in FIG. 7, it should be noted that there occurs an increase of resistance due to the serial connection of two transistors 10A and 10A′ in the discharge current path between the diffusion region 11G and the diffusion region 11C, and the current drivability of the lateral bipolar transistor is degraded. Associated with this, there occurs an increase of heating.